68HC705J2CP

Product Summary

The 68HC705J2CP is a member of the low-cost, high-performance M68HC05 Family of 8-bit microcontroller units (MCUs). The high-density, complementary metal-oxide semiconductor (HCMOS) M68HC05 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the popular M68HC05 central processor unit (CPU) and are available with a variety of subsystems, memory sizes and types, and package types. The 68HC705J2CP is an expansion of the MC68HC05J1 design. On-chip memory is enhanced with 2 Kbytes of erasable, programmable ROM (EPROM), 112 Kbytes of RAM, and a bootloader ROM.

Parametrics

Absolute maximum ratings:(1)Supply Voltage VDD –0.3 to +7.0 V; (2)Input Voltage, All Pins in Normal Operation, Vin: VSS – 0.3 to VDD + 0.3V; (3)Input Voltage, IRQ/VPP Pin in Bootloader Mode, Vin: VSS – 0.3 to 2 VDD + 0.3V; (4)EPROM Programming Voltage (IRQ/VPP Pin), VPP: 16.75V; (5)Current Drain Per Pin (ExcludingVDD and VSS), I: 25mA; (6)Operating Temperature Range, MC68HC705J2CP, CDW (Extended), TA: –40 to +85°C; (7)Storage Temperature Range, TSTG: –65 to +150°C.

Features

Features:(1)Popular M68HC05 CPU; (2)Memory-Mapped Input/Output (I/O) Registers; (3)2064 Bytes of User EPROM Including 16 User Vector Locations; (4)112 Bytes of Static RAM (SRAM); (5)14 Bidirectional I/O Pins; (6)Fully Static Operation With No Minimum Clock Speed; (7)On-Chip Oscillator With Crystal/Ceramic Resonator Connections; (8)15-Bit Multifunction Timer; (9)Real-Time Interrupt Circuit; (10)Bootloader ROM; (11)Power-Saving STOP, WAIT, and Data Retention Modes; (12)MC68HC05J1 Emulation Mode; (13)Selectable Edge-Sensitive or Edge- and Level-Sensitive External Interrupt Trigger; (14)Selectable Computer Operating Properly (COP) Timer; (15)8 x 8 Unsigned Multiply Instruction; (16)One Time Programmable 20-Pin Dual-in-Line Package (DIP); (17)One Time Programmable 20-Pin Small Outline Integrated Circuit (SOIC); (18)Windowed 20-Pin Cerdip.

Diagrams